gnupic: Possible 'gpsim' 16F877 EEPROM Data Write Bug
Subject:
Re: Possible 'gpsim' 16F877 EEPROM Data Write Bug
From:
"Tom Alldread, VA7TA" ####@####.####
Date:
17 Oct 2002 14:19:14 -0000
Message-Id: <5.1.0.14.2.20021017064153.00a187d0@mail.island.net>
Greetings Sam:
Many thanks for your input!
I don't believe the bytes stored in EEDATA and EEADR are accessed
after the WR bit is set and WREN is dropped - at least that is what the
MPSIM suggests as my code appeared to work OK in it. In any event it
doesn't make sense to disturb the EEDATA and EEADR registers before the
write process is done. I originally had the busy test loop at the very
beginning of the routine as per MicroChip's example and then in the process
of moving it around to satisfy the needs of 'gpsim' lost track of that
train of thought. I subsequently moved it down the routine a bit to save a
bank switch step. I have now moved the busy test loop back towards the top
of the subroutine as per your suggestion and MicroChip's example code. It
tests OK in MPSIM but does not run in 'gpsim'.
I have added conditional assembly statements now so I can select
either of the two A or B configurations which will permit to debug with the
much faster 'gpsim' yet easily switch back to the more optimal design prior
to programming the chip.
Thanks again!
;----------------------------------------------------------------------------------------------------------------
EXAMPLE conditional assembly code
;****************************************************************************************
EEProg: ; Program EEPROM byte - enter with data preloaded in global variables
; byte to be written in data1 & address in data0
;****************************************************************************************
bsf STATUS,RP1 ;select bank 3
bsf STATUS,RP0 ;select bank 3
IF LinuxSim == 0
EEPLoop ;ensure previous write cycle has completed
btfsc EECON1,WR ;is write cycle complete?
goto EEPLoop ;wait for write to finish
EEReady
ENDIF
btfsc INTCON,GIE ;skip next if global interrupts disabled
at entry
bsf GIEFlag ;set the GIEflag if GIE enabled at entry
bcf STATUS,RP0 ;select bank 2
movf data0,w ;get the address
movwf EEADR ;put it in EE adr register
movf data1,w ;get the data
movwf EEDATA ;put it in EE data register
bsf STATUS,RP0 ;select bank3
bcf EECON1,EEPGD ;point to data memory
bsf EECON1,WREN ;enable EEPROM write
bcf INTCON,GIE ;disable interrupts
movlw h'55'
movwf EECON2 ;write 55
movlw h'AA'
movwf EECON2 ;write AA
bsf EECON1,WR ;start write
btfsc GIEFlag ;enable interrupts only if enabled at entry
bsf INTCON,GIE ;enable interrupts
IF LinuxSim == 1
EEPLoop ;ensure previous write cycle has completed
btfsc EECON1,WR ;is write cycle complete?
goto EEPLoop ;wait for write to finish
EEReady
ENDIF
bcf EECON1,WREN ;disable writes
RtnBk0 bcf STATUS,RP1 ;select bank 0
bcf STATUS,RP0 ;select bank 0
bcf GIEFlag ;clear the GIE flag
return
;==================================================================================
At 13:37 02/10/16, you wrote:
>On 16/10, Tom Alldread, VA7TA wrote:
>
>| movf data0,w ;get the address
>| movwf EEADR ;put it in EE adr register
>| movf data1,w ;get the data
>| movwf EEDATA ;put it in EE data register
>| bsf STATUS,RP0 ;select bank3
>| ;EEPLoop ;ensure previous write cycle has
>| completed
>| ; btfsc EECON1,WR ;is write cycle complete?
>| ; goto EEPLoop ;wait for write to finish
>
>I know the busy loop is commented here, but if it was, would it be safe
>to change EEDATA/EEADR while a write operation is in progress? The
>sample code from the 16f76x datasheet tests this bit before or after the
>whole operation, not in the middle. Those registers may be used by the
>write operation.
>
> Sam
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