gnupic: Re: [gnupic] more on weird resets
Subject:
Re: [gnupic] more on weird resets
From:
John Sheahan ####@####.####
Date:
31 Jul 2005 13:17:30 +0100
Message-Id: <42ECC152.10203@optushome.com.au>
A while back, decoupling ttl inputs via a pullup was a great idea
as the damage voltage rating on inputs was less than on the collecter
supply. I don't think thats valid for cmos, as most gates are
connected to one supply - and its gate oxide that matters.
Your suggested solution works as well its a good capacitor connected to
an appropriate virtual earth.
perhaps you could explain more why a connection from VDD to the reset
input is flawed?
line pumping from spikes? positive spikes won't reset the chip for an
active low clr.
Negative spikes on VDD sufficient to cause reset with what I suggested
will drive VDD below 2xVt - so you have issues any which way. Better VDD
decoupling - my first point - is the solution here.
If we are relying on the on-chip wiring as the dominant decoupling
capacitance I guess an external cap will protect against negating spikes
on VDD. Other inputs don't work reliably here. I try not to operate my
circuits there. Is this what you are suggesting?
IO line switching ? This bounces either internal VSS up or VD down.
An external decoupler does not help here in either case.
RFI? Reducing the coupling to the reset pin is the key here. depending
on where your suggested cap is connected to - it will work as well.
I don't see any obvious cases where it works better. I do assume the
wire I suggested is not longer than the RC individual elements.
regards, john
Peter wrote:
>
>
> On Sun, 31 Jul 2005, John Sheahan wrote:
>
>> Peter wrote:
>>
>>> Put a 100 ohm resistor between your current circuit and MCLR and add
>>> a 220pF cap between MCLR and VDD directly at the chip. Also add a 5V6
>>> zener between VDD and VSS.
>>
>>
>> A piece of wire would work better.
>
>
> You are basing this on what ? The solution I suggested addresses VDD
> line pumping by spikes and MCLR/VDD decoupling. Both of these preclude
> false resets caused by ground bounces, rfi and VDD supply pumping by
> glitches in IO lines. Also, where exactly would you place your highly
> conductive (as in conducting spikes and RFI) wire.
>
> In my experience saving a flaky circuit can be hard and is in most cases
> non-intuitive. PIC based circuits are often saved by the solution I have
> indicated above.
>
> Peter
>
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