gnupic: Re: [gnupic] need pic18fxxx programmer!!
Subject:
Re: [gnupic] need pic18fxxx programmer!!
From:
John Sheahan ####@####.####
Date:
26 Jan 2006 00:22:51 +0000
Message-Id: <43D8164E.6040205@optushome.com.au>
Which Xilinx cable? DLC7?
Altera specified their byte blaster board well. I seem to recall Xilinx
did for some of them. The parallel port adapters were just level shifted
bit bashers I thought. USB devices I'm not sure about.
JTAG is pretty misunderstood.
The interface is well specified,
TDI test data in
TDO test data out
TCLK test clock
TMS test mode
and optionally TRST
the JTAG state machine is well specified. (how you wiggle tdi and tms
wrt tclk to get jtag data into and out of the chips.
newer stuff runs off low voltages, sometimes 3.3v compatible. Older
stuff ued to be 5v. usually open drain.
any jtag device should support bypass and extest instructions.
bypass allows you to daisy chain lots of devices , and discover whats
connected, and talk to whichever(s) you choose.
extest allows you to overdrive your outputs (for board test) and listen
to your inputs. This is usually specified in a BSDM file which you
should be able to get for your parts.
Board test software should read your pcb netlist and the bsdm files for
the devices, and build and run connectivity tests. So you find out if
the right devices are soldered down on good tracks.
intest can allow you to supply inputs to the chip, and check outputs.
this is much less likely to be available information.
The chip designer can supply other instructions also. Things like self
test, fpga configuration, fpga readback? flash programming.
Your guess how well that is externally specified.
john
George M. Gallant, Jr. wrote:
> I have no expectations that the code for JTAG and PIC is similiar other
> than they
> use a synchronous serial data protocol. The major differences appear to
> be:
>
> PIC: Single bidirectional data line
> JTAG: Separate data in and data out line
>
> PIC: 13Volt programming
>
> JTAG appears to be standard that allows multiple vendors to share a
> common
> electrical bus. Once inside the chip, each vendor creates it's own
> register set.
> Some provide the access info, others hide it.
>
> If you find that the Xilinx JTAG is "universal" please post your
> findings as I have
> a couple of them.
>
> George
>
> On Tue, 2006-01-24 at 21:40 -0500, Martin Klingensmith wrote:
>
>
>>I have a Xilinx JTAG cable and I have been wondering if it is compatible
>>with the other forms of JTAG, I don't know if JTAG is a standard or a
>>common acronym?
>>--
>>Martin
>>
>>George M. Gallant, Jr. wrote:
>>
>>
>>>I plan to use the JTAG for CPLD and FPGA work. I don't want to be
>>>limitted by the length
>>>of the parallal port cable. Also can use USB-2-serial on laptops.
>>>
>>>George
>>>
>>>George
>>>
>>>On Tue, 2006-01-24 at 10:28 +0800, Chen Xiao Fan wrote:
>>>
>>>
>>>
>>>
>>>>>From: George M. Gallant, Jr.
>>>>>Sent: Tuesday, January 24, 2006 9:03 AM
>>>>>
>>>>>I used slow bit/banger to build a 628 based serial unit. I then used
>>>>>that unit develop a 18f1320 unit. Currently developing at 18f2550
>>>>>that will also do jtag.
>>>>>Not very difficult and the Wisp628 provides a great starting platform,
>>>>>too bad the code isn't in C or assembler.
>>>>>
>>>>>George
>>>>>
>>>>>
>>>>
>>>>Interesting. 18F USB PICs seem to be a good choice for next
>>>>generation PIC programmers. Olin is doing one with. Wouter plans
>>>>to do another one. And PICkit 2 is already being done with
>>>>18F2550. So does GTP USB /GTP USB Lite. It is a pity
>>>>that the last one is closed source so it is only working
>>>>under Windows.
>>>>
>>>>You also mentioned JTAG. Is it for the PIC24/dsPIC33
>>>>or for other MCUs like AVR and MSP430 or LPC ARM?
>>>>
>>>>I agree with you that Wisp628A is a great start. And I also
>>>>wish that it is written in plain assembler rather than JAL.
>>>>The firmware actually fails to be built with later version
>>>>of JAL.
>>>>
>>>>Regards,
>>>>Xiaofan
>>>>
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>>>>
>>>>
>>>
>>>
>>>
>>
>>
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>
>
